The present disclosure relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to a multilayered low dielectric constant (k) cap that can be present on at least one interconnect level of an interconnect structure. The present disclosure also provides methods of forming such a multilayered cap as well as an interconnect structure including the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
Current Cu interconnect structures typically include a dielectric cap thereon which provides some degree of electromigration (EM) resistance to the interconnect structure (i.e., Cu diffusion barrier). The dielectric cap can include a nitrogen and hydrogen doped silicon carbide SiC(N,H) which is typically formed by a plasma enhanced chemical vapor deposition (PECVD) process. Such dielectric caps do not have sufficient conformal fill capacity to fill a recess in the Cu that forms during processing of the interconnect structure. As the result, prior art dielectric caps provide poor step coverage to the underlying Cu region and oftentimes seams form between the Cu region and the dielectric material, particularly at the corners of the interconnect structure between the Cu region and the adjacent dielectric material. Such a Cu interconnect structure is illustrated in the SEMs of FIGS. 1A and 1B. The presence of such seams can cause poor reliability and adhesion problems in prior art interconnect structures.